Turn IC verification challenge from a hard slog into a walk in the park by using static checks

By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for…

DFM: Still a really good thing to do!

By Simon Favre If you’re not using critical area analysis and design for manufacturing to…

2021: Time to simplify your life (or at least your workload)?

Everyone makes resolutions for a better life at the start of a new year –…

LVS Zero to Hero in 3 Easy Steps

When it comes to system-on-chip (SoC) physical verification turnaround-time, layout vs. schematic (LVS) can make…

How to get to Win-Win-Win in conflict management

By Dennis Joseph – Mentor, A Siemens Business Anyone who’s been through conflict management training…

A touchy subject: RF IC layout verification

By Neel Natekar – Mentor, A Siemens Business Radio frequency (RF) circuitry is an essential…

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and…

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation…

Interconnect Robustness Depends on Scaling for Reliability Analysis

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness…