How to get to Win-Win-Win in conflict management

By Dennis Joseph – Mentor, A Siemens Business Anyone who’s been through conflict management training…

A touchy subject: RF IC layout verification

By Neel Natekar – Mentor, A Siemens Business Radio frequency (RF) circuitry is an essential…

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and…

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation…

Interconnect Robustness Depends on Scaling for Reliability Analysis

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness…

Efficient Parasitic Extraction Techniques for Full-Chip Verification

By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC…

Collaborative SoC Verification

By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design…

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks…

Automated Chip Polishing Can Make Your Design Shine

By Bill Graupp, Mentor Graphics A more robust design creates a more reliable product, and…