How to get to Win-Win-Win in conflict management

By Shelly Stalnaker & Calibre Design staff Anyone who’s been through conflict management training understands the three basic scenarios. There’s…

Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…

Turn IC verification challenge from a hard slog into a walk in the park by using static checks

By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for IC verification flows and electronic…

DFM: Still a really good thing to do!

By Simon Favre If you’re not using critical area analysis and design for manufacturing to improve your IC yield and…

2021: Time to simplify your life (or at least your workload)?

Everyone makes resolutions for a better life at the start of a new year – why not resolve to make…

LVS Zero to Hero in 3 Easy Steps

When it comes to system-on-chip (SoC) physical verification turnaround-time, layout vs. schematic (LVS) can make or break tapeout plans. Working…

A touchy subject: RF IC layout verification

By Neel Natekar – Mentor, A Siemens Business Radio frequency (RF) circuitry is an essential component of many of the…

ECO Fill Can Rescue Your SoC Tapeout Schedule

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and re-verify late-stage changes quickly, while…

Transistor level ESD verification in large SoC designs

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help