Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help
By Matthew Hogan, Mentor Graphics Latch-up detection is challenging. Learn how automated LUP checks help you find and eliminate LUP…
By David Abercrombie, Mentor Graphics Untimely DP stitching can cause more problems than it solves, that’s why strategic use is…
By Michael White, Mentor Graphics Established nodes have a lot of dancing left to do! Learn how and why new…
By James Paris, Mentor Graphics Back-annotation of DFM enhancements to P&R simplifies iterations as designers close timing and physical verification
By Phil Brooks, Mentor Graphics Can you accurately extract device pin-specific properties without creating phantom nets?
By Michael White, Mentor Graphics Integrating pattern matching with design verification and process development yields benefits at all nodes. Learn…
By Karen Chow, Mentor Graphics Electromigration can destroy an IC before its time. Are your designs safe?
By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you correct reliability issues while they…
