Case Studies in Double-Patterning Debug: Part One

Case Studies in Double-Patterning Debug: Part One

By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their solutions may not be obvious

The Changing (and Challenging) IC Reliability Landscape

The Changing (and Challenging) IC Reliability Landscape

By Matthew Hogan, Mentor Graphics Reliability issues have gone way beyond DRC and LVS verification…

The Fill Ecosystem Evolves Again

The Fill Ecosystem Evolves Again

By Jeff Wilson, Mentor Graphics At 20nm, new fill constraints drive up the time and complexity of the fill process….

Automated Chip Polishing Can Make Your Design Shine

Automated Chip Polishing Can Make Your Design Shine

By Bill Graupp, Mentor Graphics A more robust design creates a more reliable product, and reduces yield variability over its…

Are Three Eyes Better Than Two?

Are Three Eyes Better Than Two?

By David Abercrombie, Mentor Graphics Error analysis in triple patterning is challenging, but a pyramid approach helps designers prioritize and…

Custom Layout Designers Need New Tools for New and Expanding Markets

Custom Layout Designers Need New Tools for New and Expanding Markets

By Srinivas Velivala, Mentor Graphics New debugging capabilities in Calibre RealTime can help shrink your time-to-tapeout while still ensuring high-quality…

IoT, Cost-per-Transistor Extend Lifetimes of Established Technology Nodes

IoT, Cost-per-Transistor Extend Lifetimes of Established Technology Nodes

By Michael White, Mentor Graphics Much of the Internet of Things (IoT) functionality we crave is more cost-effective when implemented…

How Close Can We Put Different Voltage Regions Together?

How Close Can We Put Different Voltage Regions Together?

By Joe Davis, Mentor Graphics  Calibre tools provide a complete flow for implementing, optimizing, and verifying voltage-dependent layouts against the…

Parasitic Extraction of FinFET-based Memory Cells

Parasitic Extraction of FinFET-based Memory Cells

By Karen Chow, Mentor Graphics Accurate and efficient FinFET characterization requires a parasitic extraction tool that can apply different extraction…