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Transistor level ESD verification in large SoC designs

Transistor level ESD verification in large SoC designs

October 31, 2016

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help

By Design With Calibre
4 MIN READ
Interconnect Robustness Depends on Scaling for Reliability Analysis

Interconnect Robustness Depends on Scaling for Reliability Analysis

June 29, 2016

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…

By Design With Calibre
5 MIN READ
The Changing (and Challenging) IC Reliability Landscape

The Changing (and Challenging) IC Reliability Landscape

September 8, 2015

By Matthew Hogan, Mentor Graphics Reliability issues have gone way beyond DRC and LVS verification…

By Design With Calibre
6 MIN READ
My Design’s Interconnect Has Enough Wire Width to Withstand ESD… Doesn’t It?

My Design’s Interconnect Has Enough Wire Width to Withstand ESD… Doesn’t It?

January 28, 2015

By Frank Feng, Mentor Graphics Electrostatic discharge can destroy a circuit, but designing adequate protection is not always a matter…

By Design With Calibre
5 MIN READ