By Derong Yan Meeting tapeout schedules and performance requirements are equally critical conditions for IC design success. Now engineers can…
By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…
By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more sensitive to the damage caused…
By Dina Medhat Electrostatic discharge (ESD) events cause severe damage to unprotected integrated circuits (ICs). You already know that, of…
By Calibre Staff Electrostatic discharge (ESD) is a big worry for integrated circuit (IC) designers, for good reason. A bit…
By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for IC verification flows and electronic…
By Abdellah Bakhali – Mentor, A Siemens Business If you’re not an ESD expert (and let’s face it, most of…
Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help
By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…
