Caution! Avoid detours when improving resistance on ESD paths

By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more…

Do you need an automated ESD verification methodology for 2.5D/3D ICs? If so, read on…

By Dina Medhat Electrostatic discharge (ESD) events cause severe damage to unprotected integrated circuits (ICs)….

ESD protection verification in 2.5/3D ICs is HARD (or is it?) Our on-demand webinar has the answer

By Calibre Staff Electrostatic discharge (ESD) is a big worry for integrated circuit (IC) designers,…

Turn IC verification challenge from a hard slog into a walk in the park by using static checks

By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for…

Help! I’m not an ESD expert! Reducing ESD verification complexity

By Abdellah Bakhali – Mentor, A Siemens Business If you’re not an ESD expert (and…

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation…

Interconnect Robustness Depends on Scaling for Reliability Analysis

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness…

The Changing (and Challenging) IC Reliability Landscape

By Matthew Hogan, Mentor Graphics Reliability issues have gone way beyond DRC and LVS verification……

My Design’s Interconnect Has Enough Wire Width to Withstand ESD… Doesn’t It?

By Frank Feng, Mentor Graphics Electrostatic discharge can destroy a circuit, but designing adequate protection…