Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

Filter by:

Latest posts

Accelerate IP design cycles and reduce costs with Calibre design stage verification

May 6, 2024

By Terry Meeks In the fast-paced world of semiconductor design, time is a critical asset. One way IC designers save…

By Design With Calibre
5 MIN READ

Balancing performance vs. debuggability in LVS circuit verification

April 23, 2024

By Wael ElManhawy Circuit verification engineers face ever more challenges as semiconductor technology evolves towards smaller process nodes and integrated…

By Design With Calibre
3 MIN READ

A new physical verification reporting solution smooths the on-time tapeout effort

April 16, 2024

By Richard Yan In the intricate world of system-on-chip (SoC) development, Physical Verification (PV) reports serve as vital checkpoints throughout…

By Design With Calibre
2 MIN READ

How to verify well layer connectivity with soft checks

April 10, 2024

By Terry Meeks In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions…

By Design With Calibre
5 MIN READ

AI/ML rules at the 2024 SPIE Advanced Lithography + Patterning symposium

April 3, 2024

The SPIE Advanced Lithography + Pattering symposiums were held from 25-29 February this year with enthusiastic and sizable attendance. The…

By Design With Calibre
2 MIN READ

Unlocking the future with a digital twin for semiconductor manufacturing

March 29, 2024

By Srividya Jayaram In semiconductor manufacturing, staying ahead means embracing smarter processes. The rise in demand and the need to…

By Design With Calibre
5 MIN READ

Using a shift left strategy to address block/chip design challenges during design-stage verification

March 21, 2024

By David Abercrombie For IC designers, striking the right balance between tight deadlines and limited resources is a constant challenge….

By Design With Calibre
3 MIN READ

How to get accurate inductance extraction for superconductor ICs

March 15, 2024

By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data centers and…

By Design With Calibre
4 MIN READ

The secret to Calibre software quality – AnaCov, our in-house code coverage analysis tool

March 7, 2024

By Mustafa Naeem, Ahmed Tahoon, Omar Ragi, and Reem El-Adawi In the realm of software testing, accurately tracking and analyzing…

By Design With Calibre
3 MIN READ