Why PID issues matter to IC chip designers, and how to combat them

By Derong Yan Integrated circuit (IC) chip designers are constantly striving to meet ever-increasing standards of reliability and performance in…

Calibre PERC checks meet Calibre RVE default views: A match made in debugging heaven?

By Neel Natekar As technology node scaling continues, integrated circuit (IC) designers are facing increasing physical verification challenges due, in…

Optimize metal fill insertion while protecting critical nets and devices…automatically!

By Dina Medhat Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly…

How can I run reliability checks early in the design cycle?

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff…

Help! I’m not an ESD expert! Reducing ESD verification complexity

By Abdellah Bakhali If you’re not an electrostatic discharge (ESD) expert (and let’s face it, most of us aren’t), verifying…

Automated common resistance checking…it’s the smart thing to do!

By Hossam Sarhan Work smarter, not harder. Isn’t that what everyone is always telling you? Of course, it’s excellent advice,…

Find high resistance faster in P2P violations with interactive P2P analysis

By Slava Zhuchenya So your net trace has too much parasitic resistance. Where is it coming from? You ran your…

Struggling to verify the reliability of your multiple-power-domain designs?

By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize…

Plug and Play ESD protection

By Mark Tawfik Electrostatic discharge (ESD) is the discharge of static electrical current when two objects come into contact. One…