Infineon and Siemens collaborate for innovation

By Karen Chow When Infineon needed to select a field solver for the development of their next-generation power semiconductor products,…

Outta my way – electrons coming through!

By Joel Mercier and Karen Chow Ever been in a hurry to get to a meeting, but there were a…

LVS Zero to Hero in 3 Easy Steps

By James Paris When it comes to system-on-chip (SoC) physical verification turnaround-time, layout vs. schematic (LVS) verification can make or…

Does your parasitic extraction work in 5G IC designs?

By Salma Ahmed and Karen Chow The next-generation 5G mobile communication network is a heterogeneous network providing significant performance advantages…

Mastering RF design challenges: The role of capacitors and context-aware PEX Tools

By Claudia Relyea and Sandeep Koranne  Updated January 17, 2025 The increasing complexity of modern RF circuits demands precise modeling…

Want to know what went on at the TSMC OIP Forum this year? Here’s the inside scoop…

TSMC customers and partners always look forward to the annual TSMC Open Innovation Platform® (OIP) Forums. Here, they get the…

Early circuit verification can get you to tapeout faster…here’s how

For the last few years, it’s been hard to see design teams struggling to meet tapeout schedules caused by increasing…

Device Pin-Specific Property Extraction For Layout Simulation

Device Pin-Specific Property Extraction For Layout Simulation

By Phil Brooks, Mentor Graphics Can you accurately extract device pin-specific properties without creating phantom nets?  

Electromigration protection requires accurate interconnect modeling

Electromigration protection requires accurate interconnect modeling

By Karen Chow, Mentor Graphics Electromigration can destroy an IC before its time. Are your designs safe?