An introduction to advanced verification techniques for IC design symmetry

By Jonathan Muirhead Integrated circuit (IC) design, particularly for analog and radio frequency (RF) circuits, involves meticulous attention to detail…

Speeding up early design rule checking with Calibre nmDRC Recon

By John Ferguson and Nermeen Hossam Chip designers are very aware of how time-consuming early design rule checking (DRC) can…

A new physical verification reporting solution smooths the on-time tapeout effort

By Richard Yan In the intricate world of system-on-chip (SoC) development, Physical Verification (PV) reports serve as vital checkpoints throughout…

Shifting left with Calibre solutions: Enhancing IP design flow efficiency and design quality

By Terry Meeks Designing integrated circuits (ICs) is a multifaceted task that requires the integration of various components, including intellectual…

3DICs and the multi-physics challenge

By John Ferguson Design teams have known since, well, pretty much forever that mechanical stresses and temperature changes can affect…

Save yourself the time—here’s a way for you to view native block instances from a full-chip context

By Ritu Walia Imagine this: You primarily work on the design of a sub-block of an application-specific layout design, or…

First out of the (3DIC) box: How Siemens EDA is using the TSMC 3Dblox standard to change 3DIC verification

By John Ferguson In recognition of the growing need for a more holistic approach to three-dimensional integrated circuit (3DIC) design,…

Fast, efficient, productive? Your early-stage IC design physical verification can be all that…

By John Ferguson and Nermeen Hossam With each new process node comes more complex requirements needed to ensure working silicon. …

Google, AMD, and Siemens EDA walk into a cloud…

By Michael White At DAC this past July, I had the opportunity to sit down with Phil Steinke from AMD…