A system-level verification engineer once told me that his company consumes over 50% of its emulation capacity debugging failures. According…
Graph-Based Intelligent Testbench Automation While intelligent testbench automation is still reasonably new when measured in EDA years, this graph-based verification…
Advanced verification techniques including functional coverage and constrained random stimulus generation have proven themselves invaluable in the design of the…
“Ready, Set, Deploy” The last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification…
Instant Replay Offers Multiple Views at Any Speed If you’ve watched any professional sporting event on television lately, you’ve seen…
Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about…
Who Doesn’t Like Faster? In my last blog post I introduced new technology called Intelligent Testbench Automation (“iTBA”). It’s generating…
iTBA Introduction If you’ve been to DAC or DVCon during the past couple of years, you’ve probably at least heard…
Testbench Characteristics and Simulation Strategies (Continued) This blog is a continuation of a series of blogs, which present the highlights…
