Effort Spent in Verification This blog is a continuation of a series of blogs that present the highlights from…
Clocking and Power Trends In Part 2 of this series of blogs, I continued the discussion focused on design trends…
Design Trends (Continued) In Part 1 of this series of blogs, I focused on design trends (click here) as identified…
Design Trends In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of…
A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is…
The latest revision of the IEEE 1800-2012 SystemVerilog Language Reference Manual (LRM) is about to hit the press; though I…
A new style takes center stage It was Fashion Week in Portland, Oregon in early October. And while the thought…
At the 2012 Design Automation Conference, I had the pleasure of moderating a panel at a workshop titled “Post-Silicon Debug:…
A system-level verification engineer once told me that his company consumes over 50% of its emulation capacity debugging failures. According…
