Static Verification

Static Verification

After spending years verifying ASICs with dynamic simulation, I started working on static verification 10 years ago in a startup…

OVM/UVM at DAC 2010

OVM/UVM at DAC 2010

Visit Booth 1350 – The hub of OVM/UVM Activity at DAC The OVM World booth at the Design Automation Conference…

DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation

DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation

I’d like to encourage you to attend the technical panel titled Bridging Pre-Silicon Verification and Post-Silicon Validation at this year’s …

UVM-EA (Early Adopter) Starter Kit Available for Download

UVM-EA (Early Adopter) Starter Kit Available for Download

Companion UVM-EA OVM Compatibility Overlay Kit Available for Download Mentor Graphics has made available its UVM-EA starter kit to promote…

Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)

Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)

Requirements set for Accellera UVM-EA (Early Adopter) Release This was a productive week for Accellera. After months of discussions, the…

OVM 1.0 Register Package Released

OVM 1.0 Register Package Released

After months of field testing and several beta releases the past few years, Mentor Graphics has released the OVM 1.0…

IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download

IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download

Just in time for the holidays!  🙂 IEEE Std. 1800™-2009, aka SystemVerilog 2009, is ready for purchase and download from…

DVCon is Just Around the Corner

DVCon is Just Around the Corner

Hi Gang, As you may know, in addition to my duties here at Mentor, I’m also the General Chair of…

SystemVerilog Coding Guidelines

SystemVerilog Coding Guidelines

I have lots of blog entries about 95% ready to publish. This entry is from an e-mail I wrote a…