A new style takes center stage It was Fashion Week in Portland, Oregon in early October. And while the thought…
OVM Bridges SystemVerilog and SystemC Languages When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog)…
Live & In-Person at DAC 2012! Verification Academy, the brain child of Harry Foster, Chief Verification Scientist at Mentor Graphics,…
Open-Source Proof-of-Concept Library Released Accellera Systems Initiative has released for general industry use an open-source proof-of-concept library as a companion…
Graph-Based Intelligent Testbench Automation While intelligent testbench automation is still reasonably new when measured in EDA years, this graph-based verification…
Where might our paths cross? It is always challenge to fit all the needed visits in during the Design Automation…
The philosophy behind our Verification Academy is to provide a comprehensive resource for evolving and maturing your functional verification process skills….
Advanced verification techniques including functional coverage and constrained random stimulus generation have proven themselves invaluable in the design of the…
In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should…
