UVM: Some Thoughts Before DVCon

UVM: Some Thoughts Before DVCon

It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the…

UVM™ at DVCon 2012

UVM™ at DVCon 2012

“Ready, Set, Deploy” The last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification…

SystemC 2011 Standard Published

SystemC 2011 Standard Published

IEEE Std. 1666™-2011 Available as Free Download In November 2011 I blogged the IEEE Standards Association (SA) approved a revision…

2011 IEEE Design Automation Standards Awards

2011 IEEE Design Automation Standards Awards

The DASC Participates in IEEE Standards Association Gala Event The IEEE Computer Society Design Automation Standards Committee (DASC) participated in…

TLM Becomes an IEEE Standard

TLM Becomes an IEEE Standard

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced…

VHS or Betamax?

VHS or Betamax?

Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about…

Verification Issues Take Center Stage

Verification Issues Take Center Stage

Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on…

Going from “Standards Development” to “Standards Practice”

Going from “Standards Development” to “Standards Practice”

Historical Perspective In my early days of standards development, I was intrigued how a standard went from the development phase…

The IEEE’s Most Popular EDA Standards

The IEEE’s Most Popular EDA Standards

How do your favorites rank? Have you ever wondered how popular the different IEEE standards for electronic design automation are?…