Part 8: The 2010 Wilson Research Group Functional Verification Study

Part 8: The 2010 Wilson Research Group Functional Verification Study

Language and Library Trends This blog is a continuation of a series of blogs, which present the highlights from the…

User-2-User’s Functional Verification Track

User-2-User’s Functional Verification Track

User Adoption of OVM Featured; Views on UVM Discussed The Mentor Graphics user group meeting, User-2-User, in Santa Clara is…

IEEE Standards in India

IEEE Standards in India

IEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi I, along with several other individuals, will participate…

Accellera Approves New Co-Emulation Standard

Accellera Approves New Co-Emulation Standard

Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the…

Towards UVM Register Package Interoperability

Towards UVM Register Package Interoperability

23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package As readers of the…

UVM: Joint Statement Issued by Mentor, Cadence & Synopsys

UVM: Joint Statement Issued by Mentor, Cadence & Synopsys

DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys The full statement can be read at EDA…

OVM/UVM at DAC 2010

OVM/UVM at DAC 2010

Visit Booth 1350 – The hub of OVM/UVM Activity at DAC The OVM World booth at the Design Automation Conference…

Accellera’s DAC Breakfast & Panel Discussion

Accellera’s DAC Breakfast & Panel Discussion

UVM: Charting the New Territory At this year’s DAC, Accellera introduces UVM (Universal Verification Methodology) to the world at its…