Circuit board with chip and binary data depicting interface Protocol Verification

Announcing Avery UCIe 2.0 Verification IP from Siemens EDA

Announcement: Siemens EDA are excited to announce availability of our Verification IP products for UCIe version 2.0, coincident with today’s…

Accelerating Verification of Computational Storage Designs (NVMe)

Introduction Computational storage is revolutionizing data storage by embedding computational capabilities within storage devices, significantly boosting system efficiency by reducing…

Join us at Accellera’s DAC Luncheon to discuss PSS

Portable Test & Stimulus Standard Takes Center Stage at Accellera’s DAC Luncheon.  The luncheon will be held on Tuesday, June…

Accellera Day at DVCon U.S. 2024

DVCon U.S. 2024 will be a week packed with paper sessions, tutorials, panels, keynotes and more on the latest in…

Join us at DVCon for a panel on Generative AI

It’s that time of year again, and I couldn’t be more excited for the 2024 Design & Verification Conference &…

Welcome to the enhanced Verification Academy 2.0 forums!

We’ve recently enhanced the Verification Academy, moving to an all new platform. The Verification Academy is the industry’s leading resource…

Welcome to Verification Academy 2.0!

Step into the enhanced Verification Academy 2.0! After a year of meticulous development, we are thrilled to unveil its array…

IEEE Honors Siemens Employees for Dedication to Standards Development

Annually, the IEEE Standards Association (IEEE SA) recognizes outstanding participation across a variety of technical areas of standards development, leadership,…

Siemens EDA VIP at Flash Memory Summit

Come and see what Siemens EDA’s Verification IP experts are talking about at the Flash Memory Summit event. This annual…