Siemens EDA at FMS 2025 – Shaping the Future of Memory and Storage

We’re excited to connect with fellow innovators, engineers, and industry leaders at FMS 2025. Whether you’re attending our sessions or stopping by Booth #1140, we look forward to sharing the latest technical advancements in verification IP, system-level validation, and memory and interconnect technologies.

Industrial-Grade AI in EDA: From Promise to Practice — A Siemens Panel at DAC 2025

Industrial-Grade AI in EDA

First-Silicon Success

Generative AI: The Hype, The Hope, The Hard Truths — And the Debate at DAC

The semiconductor industry is no stranger to bold claims. But few topics today spark more debate — or more genuine…

From Rule-Based Beginnings to AI-Driven Design: Tracing the Evolution of AI in EDA

As we gear up for the 62nd Design Automation Conference (DAC) in San Francisco, one of the most anticipated events…

Questa One DFT Verification

DFT Verification: Tackling the evolving challenges

Technological advancement continues as a blistering pace, and the demand for highly reliable systems is paramount across various industries. Safety…

User2User

Closing the Gap in Software Skills for Verification Engineers

I’m excited to announce next month’s U2U (User-to-User) meeting, followed by a crucial technical training session that no hardware verification…

DVCon 2025: A must for hardware design and verification engineers

I’ve attended every DVCon US conference since its inception, over 30 years ago. I’ve also given keynotes at DVCon India….

Siemens at DVCon 2025: Don’t Miss the Luncheon and More!

The latest trends in verification are in—and they’re more than just surprising. They’re alarming. Join Siemens EDA at DVCon 2025 for an exclusive luncheon…

Update from the Standards World: Accellera Approves UVM-MS 1.0 Standard

Accellera Systems Initiative approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard.  This milestone marks a significant advancement in…