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Portable Test – Portable Intent, Portable Realization, or Both?

Portable Test – Portable Intent, Portable Realization, or Both?

The Accellera Portable Stimulus Working Group (PSWG) has been hard at work defining a language specification for capturing portable test…

Mentor Leads Portable Stimulus at DVCon US

Mentor Leads Portable Stimulus at DVCon US

I think I’ve mentioned before that DVCon (now DVCon US) is one of my favorite times of year. Having a…

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the issues raised below, as well…

See You at DVCon U.S. 2018!

See You at DVCon U.S. 2018!

We hope to see you at DVCon U.S. 2018.  Mentor will showcase 17 papers and posters during the conference on…

Debugging Complex UVM Testbenches

Debugging Complex UVM Testbenches

Modern complex chips necessarily have modern complex testbenches. The testbenches of old – wiggling one pin at a time and…

SystemVerilog Standard Updated

SystemVerilog Standard Updated

The latest revision to the SystemVerilog standard, IEEE 1800™-2017 was approved at the December 2017 IEEE Standards Association meeting series. …

New Verification Horizons Issue Available

New Verification Horizons Issue Available

Our special year-end issue of the Verification Horizons Newsletter (for which this blog is named, by the way) is now available!…

Developing Tests in Reverse with Portable Stimulus

Developing Tests in Reverse with Portable Stimulus

Whether developing tests for software or hardware, test development seems to follow a pretty predictable process: learn about the thing…

Formal Tech Tip: What are Vacuous Proofs, Why They Are Bad, and How to Fix Them

Formal Tech Tip: What are Vacuous Proofs, Why They Are Bad, and How to Fix Them

In formal verification, proving all of your properties is pretty much the main goal of the whole exercise – if…