Thought Leadership

New and Improved SystemVerilog 1800-2017

February 23, 2018 • 3 MIN READ
By Dave Rich

The IEEE-SA has a policy of keeping standards active by making sure they get a cycle of updates every 10 years. Including Verilog, SystemVerilog has been going on a cycle of updates every 5±1 years since 1995. I wrote here about the updates to 1800-2009 and 1800-2012, and now I’m writing about the upcoming release of 1800-2017.

So, what’s new and improved in the 1800-2017 standard?

The standard is new and improved. By that I mean the document that supposedly describes the behavior of the code you write. It resolves over 100 issues and probably 100s of editorial issues. Does this sound exciting? Probably not to most people. But here are the benefits and why it may be exciting to you:

  • No new features to learn that you will never remember how to use anyway
  • No forward or backward compatibility issues with your code from different versions of the standard.
  • A document more accurately reflecting the behavior you are already getting from your tool
  • Updated examples reflecting the recommended way of using SystemVerilog

For example, one issue defines the behavior of a call to a virtual method in a constructor. Different languages handle this inconsistently. Some do not allow it, others only consider it virtual up to the point where the method gets called from the constructor. Or does it call the fully extended method base on the final constructed object?  The problem is the construction and initialization of a class object always starts at the base class and works its way up to the actual extended class. In the following code, when you construct class B, the call to print() from the base class constructor is now defined to call the print method B. But be aware, the values it displays for m and n will be 1 and 0 because the extended class B has yet to be initialized.

It’s a lot more work releasing a standard with no enhancements than you might think. It’s hard getting participation in a group tasked with just making clarifications and fixing bugs. People naturally want to be creative, and as engineers, love to add features. But in the end, I think this revision of the standard serves end users very well. They want to have a document that reflects the behavior they see in their tools.

What makes me say this?

I track all the articles I’ve written on this blog covering many different SystemVerilog topics. Surprisingly, there’s one article that consistently gets more hits than any other article on the site: What’s the deal with those wire’s and reg’s in Verilog. Users still struggle with one of the most basic concepts of Verilog from its initial release in 1985. Many users (and teachers) have yet to adopt many of the features from Verilog-2001 that were supposed to make writing HDL code easier. So, do we really need to add more features to the language to make people more productive?

Of course, the answer to that is always going to be yes. In fact, tool vendors are constantly correcting and extending SystemVerilog support without waiting for a new standard. It’s the nature of the industry and a tough balancing act.

Dave Rich

Dave Rich is Verification Technologist at Mentor Graphics and is one of the authors of Mentor’s Advanced Verification Methodology cookbook. He began his career as a design and verification engineer in 1981 at Data General. In 1987, he joined Gateway Design Automation as one of the first application engineers to support Verilog-XL. At Gateway, he helped design many of the early features of the Verilog Hardware Description Language (HDL), and after Cadence acquired Gateway, helped prepare the Language Reference Manual (LRM) that would eventually be donated to the newly formed Open Verilog International. In 1995, he joined another Verilog simulation company, Frontline Design Automation as an AE manager and later as a Product Manager after it was acquired by Avant!. In 1998, he joined Ambit Design and worked as a consulting engineer for both synthesis and simulation products after it was acquired by Cadence. In 2000, he joined Co-Design Automation as Director of Application Engineering where the Superlog HDL was being developed that eventually became the basis of the Accellera SystemVerilog 3.0 standard. Co-Design Automation was acquired by Synopsys in 2002. Dave began work on numerous technical committees within Accellera and later the IEEE P1800 working group, which he continues today.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/verificationhorizons/2018/02/23/new-and-improved-systemverilog-1800-2017/