Verification Horizons

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Deploying HLS into a DO-254/ED-80 workflow

March 30, 2021

To remain competitive in a challenging market, avionics companies continue to innovate across all aircraft-related systems, including flight management, communication,…

By Jake Wiltgen
2 MIN READ

Siemens EDA launches new Veloce hardware-assisted verification system

March 26, 2021

Siemens Digital Industries Software today unveiled its next-generation Veloce™ hardware-assisted verification system for the rapid verification of highly sophisticated, next-generation integrated circuit (IC) designs. This is the first complete, integrated offering that combines best-in-class virtual platform, hardware emulation, and Field Programmable Gate Array (FPGA) prototyping technologies and paves the way to leverage the latest powerful hardware-assisted verification methodologies.

By Dennis Brophy
< 1 MIN READ
TinyALU and its BFMs

Cocotb Bus Functional Models

March 22, 2021

In this series we’re talking about using Python as the testbench software in this testbench diagram: The testbench software uses…

By Ray Salemi
4 MIN READ

Getting Started with Questa Memory Verification IP

March 18, 2021

By Chris Spear & Kamlesh Mulchandani  Introduction The best way to create a System on a Chip is with design…

By Chris Spear
3 MIN READ
Proxy-Testbench

Introduction to Coroutines

March 11, 2021

In the first post of this series on Python verification we discussed the proxy-driven testbench and how a proxy-driven architecture…

By Ray Salemi
2 MIN READ
Now Available: Verification Horizons - March 2021

DVConUS Issue of Verification Horizons is Now Available

March 2, 2021

I’m pleased to announce that our March, 2021 issue of Verification Horizons is now available, just in time for DVCon…

By Tom Fitzpatrick
2 MIN READ

Finding FUN – DPI-C Recording C Variables in a Wave Database

February 18, 2021

Pandemic? Cold freeze? No Power? Ugh. What a 12 months. And all that’s unfolded. I’m looking for some fun. I…

By Rich Edelman
3 MIN READ

Getting Started with Questa Verification IP for Protocols

February 18, 2021

The best way to create a System on a Chip is with design IP: blocks that perform common functions such…

By Chris Spear
2 MIN READ

Epilogue: The 2020 Wilson Research Group Functional Verification Study

February 18, 2021

This is the last in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group…

By Harry Foster
3 MIN READ