Among the reasons to go to university are the opportunities to open new career paths by learning new technical skills, as well as socializing with other students. Attendees of the upcoming Design Automation Conference (DAC) in San Francisco from December 6–8, will get to do both. We invite you to take your knowledge to new heights with Siemens EDA Static & Formal Verification University, where verification experts will present on a wide variety of topics and hold office hours. There will also be faculty-student socials throughout the conference.
Here are the classes you can take:
Presentations in the Siemens EDA booth (2nd floor, #2521)
- Equivalence Checking for FPGA flows – Monday December 6, 3:30PM
- “The Dog Ate My RTL” Doesn’t Work Anymore – Tuesday December 7, 2:00PM
- Formal 101 – Fast, Scalable Formal Verification Made Easy – Wednesday December 8, 2:00PM
DAC Designer Track session (2nd floor Rooms 2010 and 2012)
Ensuring Completeness of Formal Verification with GapFree: Are we done yet? — Tuesday December 7, 11:22AM
DAC Poster Session (2nd floor, area 2367)
- Beyond Lint – Monday December 6, 5:00pm – 6:00pm
- Formal Verification of Safety Mechanisms – Tuesday, December 7, 5:00pm – 6:00pm
- Ensuring Completeness of Formal Verification with GapFree: Are we done yet? – Tuesday December 7, 5:00pm – 6:00pm
- Attaining Consistent RTL Quality and Improving Development Cycles with GIT Continuous Integration Tools – Wednesday December 8, 5:00pm – 6:00pm
- Verifying Reset and Power Domains Together (preventing issues being introduced by UPF) – via Virtual DAC
Office hours with static and formal verification technologists are open for the duration of the DAC expo floor hours: Monday December 6 through Wednesday December 8, from 10:00 AM to 6:00PM. Contact McKenzie at email@example.com to setup a private meeting.
Finally, start your day in the Siemens EDA booth (2nd floor, #2521) with a caffeine jolt from our handcrafted espresso bar, and then stop by the OneSpin: A Siemens Business booth (1st floor, #1539) in the afternoon for wine and cheese from California’s Napa Valley. Both spaces offer comfortable lounges where you can mingle and catch up with likeminded verification enthusiasts.
Joe Hupcey III,
Siemens EDA Static & Formal Verification University
P.S. For in-depth instruction on RISC-V focused topics, be sure to visit our colleagues in the RISC-V Pavilion (2nd floor, Booth B7)