Worst case analysis is often a self-fulfilling prophecy: By preparing for the worst you actually make it happen. In our…
Given the dramatic increase in the scalability of formal engines over the past 5 years, “formal testbenches” have grown to…
Thus far we have talked about the importance of having a VIP which is easy to connect to the DUT…
Portable Stimulus Specification tends to bring to mind applications where a given verification scenario needs to be reused across multiple…
Random hardware faults – i.e. individual gates going nuts and driving a value they’re not supposed to – are practically…
Verification Academy Brings “UVM Live” to the Santa Clara Convention Center For everyone involved in the functional verification of electronic…
Join us to review the first public review of the Debug Data API specification! At DAC 2015 we introduced Verification…
Design and verification flows are multifaceted and predominantly built by bringing tools and technology together from multiple sources. The tools…
Now that summer is over and the kids are settled into their classrooms, it’s a great time for grown-ups to…
