3 Things About UPF 3.0 You Need to Know Now
UPF 3.0 has been an official IEEE standard since January, but its most valuable capabilities have only become clear as EDA vendors and users have begun to incorporate the corresponding design & verification (D&V) features. Looking across our user base, the following three items have come to the forefront of the UPF 3.0 adoption wave. Each of these topics will be covered in the upcoming DVCon India tutorial on “Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs”, but here is a sneak preview so you can be prepared to ask the presenters more in-depth questions.
1 – Power Intent Abstraction enabled by Successive Refinement: this UPF 3.0-enabled methodology eliminates one of the biggest unintentional limitations of prior UPF versions — in the past designers were stuck defining their power intent in very specific detail, and without the ability to perform hierarchical composition of power states nor refinement of power states of an IP to fit within the SoC context. While this is OK if you are working at the implementation level, it was impossible to effectively abstract the power intent to higher levels to facilitate early and comprehensive verification. Specifically, this meant that IP creators and users had to do a lot of editing & scripting to give some semblance of flexibility to their D&V flows, and verification often had to wait till all the implementation details were known. Now, with UPF 3.0, an IP provider can capture the low power constraints for an IP block without limiting the IP consumers and back-end implementers to any particular configuration. As long as the constraints are met, the IP user can configure the IP for their particular application with ease.
2 – Automation of Power-Aware Static & Dynamic Checking: the “completeness” possible with a UPF 3.0 power intent specification, combined with the DUT’s RTL (and attributes from Liberty, if so desired) enables a unified view of the design’s power management architecture. In turn, this enables static checking of the power architecture, dynamic power sequence checking, as well as power-aware clock domain crossing (CDC) analysis. In plain English, EDA tools can now automatically find power management issues from the basic (e.g., Are the isolation cells inserted where required by power state definitions?) to the pretty-much-impossible-to-do-by-hand, exhaustive, power-aware CDC analysis for metastability risks when different asynchronous clocks crisscross different power domains.
3 – Automation of Power-Aware Functional Coverage: another valuable benefit of UPF 3.0 is the way it enables automatic power state coverage. From power state entry, to exit, through all the legal transitions, to cross-state coverage, the verification of all of these behaviors can be automated thanks to parsing of the “add_power_states” spec created by the designer. Plus, debug and analysis is no longer a matter reading tea leaves from a jumble of waveforms and log files. Instead, graphical views of circuit activity over time can clearly show the flow of power states as each DUT use case is verified, with all the results being stored in an IEEE standard Unified Coverage Database (UCDB) file for export to verification planning and management tools.
While there is much more to UPF 3.0 than these three items, it bears repeating that these have been in the vanguard of UPF 3.0 adoption by the companies on the cutting edge of low power D&V. Fortunately, the upcoming DVCon India tutorial will provide much greater detail on these flows and more so you can learn how this new generation of the UPF standard can help you meet your project’s goals faster and more effectively.
Until then, may your coverage be high and your power consumption be low,
Joe Hupcey III