DVCon Europe celebrates its 10th anniversary this year! What started as a small conference to complement DVCon in the United…
Attention anyone interested in Formal Verification: We are thrilled to invite all formal verification enthusiasts to osmosis 2023, the premier…
Introduction The space sector continues to experience disruption as innovation drives the creation of new business models across government and…
Introduction What happens when you start your simulation with a UVM test bench? Where should you put the uvm_config_db::set() calls…
Where can you improve your verification skills? In March 2023 I attended DVCon US, the Verification and Design Conference in…
What are Large Language Model’s hallucinations. LLMs will be powerful EDA productivity tool once we know what caused it and how to deal with their adverse effects.
Please mark your calendars for the highly anticipated 60th anniversary Design Automation Conference (DAC). The 60th DAC will take place…
I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this…
Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a…
