Thought Leadership

A Hitchhiker’s Guide to DVCon US ’23

By Chris Spear
DVCon US 2023

Where can you improve your verification skills?

In March 2023 I attended DVCon US, the Verification and Design Conference in San Jose, California. There were many excellent presentations, and these are my top picks, as a digital verification guy. You can see the complete program and search the proceedings for all papers across all DVCon conferences. The links below are for the papers, use search to find the presentations.

My picks for the best DVCon verification papers, 2023

The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db_API – The uvm_config_db probably confuses more UVM users than anything else, with 5 arguments, static methods, and mix of wildcard strings and component instance names. This utility is built on the uvm_resource_db class. Cliff gives a great argument why the uvm_resource_db is the better choice for sharing configuration information. I think any marginal gain is outweighed by loss in reusability as so few people know this alternative. Read this well-researched paper, learn more about these two approaches, and make your own choice.

Avoiding Configuration Madness The Easy Way – Not only is the uvm_config_db confusing, but it is the biggest performance sink in the library. Rich Edelman takes on the challenge of creating a replacement that is easier to use and faster. Definitely worth a read!

Tree Data Framework for Code Generation: Application of Generating UVM Testbench for Complex Designs – UVM testbenches are complex, but follow several basic patterns. There are many automatic testbench generators available, and most require describing the design stimulus. This paper describes the Gingko tool that extracts design information from an FSDB to speed up this first step. My main concern is that the usefulness of these generators depends directly on the maturity of the code templates.

Strategies to Maximize Reusability of UVM Test Scenarios in SoC Verification – Moving up from testbench creation, this paper shows how to create virtual sequences starting with a high-level description by refactoring your sequence library.

Regvue: Modern Register Documentation – You need to describe the hundreds or thousands of registers in your design, and share the information with coworkers. This open-source software uses modern web-based technologies to provide a more rich register documentation experience.

What’s Next for SystemVerilog in the Upcoming IEEE 1800 standard – Every language must evolve to improve and stay relevant. Dave Rich gives a great overview of the proposed changes for SystemVerilog 2024, including extending coverpoints and the array mapping function.

Creating 5G Test Scenarios, the Constrained-Random way – You may think your stimulus is complex to describe and randomize. This paper describes 5G traffic, made of resources spread across multiple channels, times, frequencies, and users, and how to generate random scenarios, requiring 5-dimensional structures.

It’s Not Too Late to Adopt: The Power of UVM – Have you started verifying your designs with UVM, and want to go deeper? I liked how this presenter is helping expand UVM adoption, along with techniques such as incremental compilation and simulation snapshots. Not every paper needs to be only for verification “rocket scientists”.

Verifying RO registers: Challenges and the solution – Verifying a register operation is easy, right? Run a sequence that sets the register and checks its value.  Except, what happens when you are not sure when the register changes, only knowing a window of time? Read this paper for some great ideas.

Live conferences are more than papers

Back in March 2020, I left DVCon early as California and the world shut down. (I learned my lesson back in 2000 when I almost got stranded in Singapore when SARS hit.) Returning after 3 years of remote work, I was excited to meet the presenters and attendees, making this conference even more valuable. The time in the hallways between sessions, and after hours was as beneficial as the papers. You should consider attending the DVCon meetings in China, Europe, India, Japan, and Taiwan.

Learn More

You can learn more about verification with Siemens courses such as SystemVerilog for Verification, UVM, UVM Intermediate, UVM Framework, and more. They are offered in instructor-led format by our industry expert instructors, or in a self-paced on-demand format. It can also be tailored to address your specific design goals and show you how to set up an environment for reuse for additional designs.  Also, you can now earn a digital badge/level 1 certificate by taking our Advanced Topics Badging Exam. This will enable you to showcase your knowledge of this topic by displaying the badge on your social media and in your email signature.

Leave a Reply

This article first appeared on the Siemens Digital Industries Software blog at