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Test technologies enabling AI

Test technologies enabling AI

At the Silicon Valley DFT and Test Conference in Santa Clara, CA on October 23, the tight-knit community of DFT…

50 Years of International Test Conference

50 Years of International Test Conference

In 1970, the Beatles officially split, Apollo 13 narrowly averted disaster, paisley and stripes somehow went together, and the International…

Video tutorial: How to Increase Volume Scan Diagnosis Throughput by 10X

Video tutorial: How to Increase Volume Scan Diagnosis Throughput by 10X

Performing volume scan diagnosis on today’s large, advanced node designs puts outsized demands on turn-around-time and compute resources. Mentor offers…

Master the design and verification of next gen transport: Part Two – high-level synthesis

Master the design and verification of next gen transport: Part Two – high-level synthesis

Excerpt from article: “Master the design and verification of next gen transport: Part Two – high-level synthesis” Part one of…

AI Hardware Summit, Report #2: Lowering Power at the Edge with HLS

AI Hardware Summit, Report #2: Lowering Power at the Edge with HLS

Excerpt from article: “AI Hardware Summit, Report#2: Lowering Power at the Edge with HLS” I previously wrote a blog about a…

Master the design and verification of next gen transport: Part One – overview

Master the design and verification of next gen transport: Part One – overview

Excerpt from article: “Master the design and verification of next gen transport: Part One – overview” The role of high-level…

Employing a Hierarchical Methodology for SoC Testing

Employing a Hierarchical Methodology for SoC Testing

When faced with a complex problem, engineers often employ a divide and conquer approach to efficiently come up with a…

DeepChip: Badru wants PnR users to know Nitro-SoC is alive and well and #3!

DeepChip: Badru wants PnR users to know Nitro-SoC is alive and well and #3!

Excerpt from article: “DeepChip: Badru wants PnR users to know Nitro-SoC is alive and well and #3!“ John, John, John……

FPGA Design Tradeoffs Getting Tougher

FPGA Design Tradeoffs Getting Tougher

Excerpt from article: “FPGA Design Tradeoffs Getting Tougher” FPGAs are getting larger, more complex, and significantly harder to verify and…