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3D IC Test: Now and the Road Ahead

3D IC Test: Now and the Road Ahead

By Martin Keim, Mentor Graphics What’s new in 3D IC testing? This summary from an ISTFA tutorial has the answers

Take scan test out of the critical path

Take scan test out of the critical path

By Ron Press, Mentor Graphics DFT with less risk to your design flow? Here’s how.  

Test Pattern Retargeting in 3D SICs using an IEEE 1687 based 3DFT architecture

Test Pattern Retargeting in 3D SICs using an IEEE 1687 based 3DFT architecture

Retarget your 2D test to 3D with IJTAG

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

Hierarchical DFT: How to Do More, More Quickly, with Fewer Resources

By Rick Fisette, Mentor Graphics Is DFT a barrier to tapeout? Time to consider going hierarchical.

Automotive Semiconductor Test

Automotive Semiconductor Test

By Steve Pateras, Mentor Graphics Ensure quality and reliability in automotive ICs with the newest technologies in silicon test.

Memory BIST for automotive designs

Memory BIST for automotive designs

By Steve Pateras, Mentor Graphics Memory BIST is evolving to meet the demands of automotive ICs.  

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

By Beth Martin with Steve Pateras, Mentor Graphics Mentor’s novel EDT test point technology dramatically reduces ATPG pattern volume

Cell-aware test can be “Awarding”

Cell-aware test can be “Awarding”

By Ron Press, Mentor Graphics Inventing Cell-aware ATPG earned Mentor’s Friedrich Hapke the 2015 Bob Madge Innovation Award.

A flexible flow for inserting embedded compression logic in RTL

A flexible flow for inserting embedded compression logic in RTL

By Ron Press, Mentor Graphics Inserting test compression logic just got a lot easier.