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Control test cost with low pin count test

Control test cost with low pin count test

By Rahul Singhal – Mentor, A Siemens Business Several design trends, including increased design sizes and the use of advanced…

The growing presence of IC Test and Yield Analysis at DAC

The growing presence of IC Test and Yield Analysis at DAC

DAC was once the playground for the core EDA topics but has broadened in a reflection of the growing connectedness…

Yasa! Mentor Focus at the European Test Symposium

Yasa! Mentor Focus at the European Test Symposium

The IEEE European Test Symposium  takes place from 22-16 May in Limassol, Cyprus. When not contemplating the stunning azure Mediterranean,…

Scan Insertion for better ATPG

Scan Insertion for better ATPG

By Vidya Neerkundar, Mentor Graphics Good scan insertion can make a difference in the quality of your automatic test pattern…

An In-Depth Interview with Dr. Walden Rhines

An In-Depth Interview with Dr. Walden Rhines

Technical innovation, EDA market growth, the value of industry consortiums, how trends such as big data impact the semiconductor industry…

U2U 2017 – See you there!

U2U 2017 – See you there!

Mentor’s user group event this year is located at the Santa Clara Marriott on April 4, 2017. Here’s what you…

What the DFT! A shortcut to hierarchical DFT

What the DFT! A shortcut to hierarchical DFT

By Ron Press, Mentor Graphics The no money down, no design change way to benefit from hierarchical DFT

Smarter Benchtop Test for Reduced Turnaround Time

Smarter Benchtop Test for Reduced Turnaround Time

Use bench-top ATPG bring-up to better understand and interact with silicon bring-up test data and reduce silicon bring-up cycle time….

A Full Life-Cycle View of Automotive Test

A Full Life-Cycle View of Automotive Test

By Steve Pateras, Mentor Graphics Ensuring safety and reliability of automotive ICs takes a full life-cycle view of automotive test…