U2U: Sneak peak at what’s to come

By Tessent Solutions

The User2User season kicks off on May 15 in Santa Clara. U2U is a free, highly interactive technical conference that focuses on real-world experiences using Mentor tools. U2U features two keynotes, nine different user-led technical tracks, product roadmap updates, a usability lab, demos, four foundry partners on site, a closing reception.

Dr. Wally Rhines presents a keynote on how semiconductor specialization drives new industry structure. Stay in your seats to catch the keynote from Broadcom’s Hooman Moshar.

Among the technical sessions, Tessent DFT and Yield offers six  presentations by leading semiconductor customers:

Dealing with Growing Design Complexity: Hierarchical DFT for Multicore Design — Juhee Han, Samsung Electronics

The size and complexity of designs necessitate new methodologies to efficiently design and apply production test patterns. We will show how hierarchical DFT using Tessent TestKompress can greatly simplify test challenges for modern designs. Instead of waiting for the full chip design for pattern generation, patterns are created as soon at the block or core is ready. With this methodology, patterns are created earlier in the design flow in much smaller design segments.

ATPG at the core level is ten times faster, uses ten times less compute resources, and is moved out of the critical path to tapeout. Tessent TestKompress uses pattern retargeting to map the core patterns to the top level automatically while adjusting for inversions and pipelines.   Moreover, an input channel sharing scheme for identical cores is also implemented to increase  pattern efficiency. The pattern retargeting and input channel sharing results in significant pattern reduction in a multicore design. Tessent TestKompress hierarchical DFT flow is available in the Samsung Foundry 8LPP process reference flow. The reference flow also includes diagnosis that understands the hierarchical ATPG pattern sources. Diagnosis patterns are automatically mapped from the chip tester failures to the core so the physical diagnosis runs faster on the failing core.

Handling Memory Signals Related to Timing and Power — Jeffrey Hung, Microsoft

Besides typical signals that govern logical reads and writes, modern memories may pave ports to control a variety of other parameters such as self-timing circuitry, low-leakage sleep/shutdown modes, and timing margin controls. However, traditional memory BIST models may describe the function of the signals as “None,” leaving it up to the user to implement and verify the proper controls and connectivity in both MBIST and functional contexts. For instance, it is often desirable to have margin bits controllable by registers, or test that allows low-leakage sleep modes that do not corrupt memory data. Ad-hoc methods can be tedious, error-prone, and do not scale well to large numbers of memories. Tessent Shell makes it straightforward to add IJTAG Test Data Registers to control these signals during memory BIST insertion, exercise them in pattern generation, and even automate constraint generation for connectivity checking with tools like Questa Formal Connectivity Check.

Case Study on Low Pin Count Testing of Industry Transceiver Chip — Imtiaz Ahmed, Qualcomm

IC designs have been growing exponentially in size, but the number of pins has not kept the same pace. This imbalance poses a difficult challenge when a design has a very limited number of test pins but still requires high-quality testing. This problem expands when additional fault models like transition delay fault model are required for testing. This paper describes how a low-pin-count test controller was able to meet all these requirements to test a pin-limited industry analog transceiver chip. The low-pin-count test controller supports at-speed testing with on-chip clock controller and exceeded the test coverage requirements for both stuck-at and at-speed testing by 1.22% and 2.16% respectively. During wafer testing, this test-pin savings using this solution enabled higher parallel of dies using multi-site testing which reduced the test-costs by about 1.5 times.

DPPM Reduction with Defect-Oriented Tests for Advanced FinFET Technology — Will Howell, Intel

This paper presents DPPM reduction results achieved by applying new Defect-Oriented Test (DOT) methods/patterns to designs manufactured in advanced FinFET technologies. The focus of this paper is on Timing-Aware Cell-Aware Test (TA-CAT) patterns targeting small delay defects of FinFET transistors, and a new DOT method which explicitly targets chip layout dependent cell-neighborhood defects. Test results from traditional Stuck-at/Transition patterns, from traditional CAT patterns, from TA-CAT patterns, and as well from Cell-Neighborhood patterns applied to FinFET technology designs will be presented in this paper. In addition, a correlation to System-Level-Test fails will be discussed.

Full Stack DFT using Tessent — Karthik Subramanian, Ambarella Corporation

The realm of DFT encompasses a large set of techniques including, but not limited to, memory BIST, memory repair, scan, compression (EDT), ATPG, boundary scan, and diagnostics, and is now making rapid forays into in-system testing. State-of-the-art SoCs require implementation of this full stack of DFT techniques to guarantee quality and reliability and the Tessent tool suite offers an integrated approach to achieve this. In this session, we summarize our experience in implementing full-stack DFT using Tessent, the many novelties of the tool suite, some of the challenges we faced and a few case studies of how we tuned the solutions offered by Tessent to meet our goals.

DFT Flow Using Tessent Shell for GHz Class IP Cores — Srinivasulu Alampally, Broadcom

High-speed IPs have several DFT challenges: support multiple levels of physical hierarchy, support for multiple voltage and power domains, tight constraints on DFT area, clock and test power. This presentation describes how Tessent DFT solutions were used in designing DFT solution conforming to above challenges, specifically for:

  • Shared bus memory BIST for memory BIST
  • Hierarchical DFT with Tessent IJTAG and scan

The paper also demonstrates some of the techniques used that were made possible with the customization capabilities of Tessent DFT solutions.

As always, we invite you to wrap up the day comparing notes and socializing with your colleagues at the closing reception that features an open bar, snacks, and drawings for great prizes.

Register now for Mentor’s User2User!




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This article first appeared on the Siemens Digital Industries Software blog at