STCO

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The smart path to STCO with Hierarchical Device Planning (HDP)

February 20, 2026

Siemens partnered with Intel Foundry to develop a STCO centric capability that enables a “smart path” to homogeneous disaggregation using Hierarchical Device Planning and parameterized pin regions.

By Keith Felton
2 MIN READ
chiplet integration with STCO system technology co optimization

Resolving Design Fragmentation Challenges in Chiplet Integration with STCO

May 11, 2025

Are you struggling to integrate chiplets into an advanced packaging platform due to design fragmentation challenges? The complexity of managing…

By Tova Levy
< 1 MIN READ

The evolution of machine learning (ML) in the physical design and verification of semiconductor packages

August 14, 2024

Discover how Siemens’ EDA evolution of machine learning in the physical design and verification of semiconductor packages.

By John McMillan
2 MIN READ

Impacts of 3D IC on the future

December 20, 2023

3D IC technology development started many years ago well before the slowing down of Moore’s law benefits became a topic…

By John McMillan
3 MIN READ
system technology co-optimization

Shifting left with system technology co-optimization for IC packaging

August 17, 2023

We have witnessed and learned about the industry’s significant shift in semiconductors. The traditional approach of transistor scaling, once universally…

By Keith Felton
3 MIN READ
Illustration of 3D IC design workflows

Why co-design-driven semiconductor package planning and prototyping is critical for design success

April 20, 2023

The connectivity management complexity of package assemblies where multiple chiplets/ASICs and memory are heterogeneously integrated, introduces a great deal of…

By Keith Felton
3 MIN READ