The evolution of machine learning (ML) in the physical design and verification of semiconductor packages

Discover how Siemens’ EDA evolution of machine learning in the physical design and verification of semiconductor packages.

User2User 2024: EMIB based advanced packaging flow – Intel Foundry

Learn how Intel uses 3DIC verification to leverage Siemens XSI & Calibre 3DSTACK for DRC, LVS, assembly checks. Explore methodologies for high-performance systems.

Why is a comprehensive workflow essential for chiplet design and today’s 3D IC architectures?

Explore this infographic to learn why a comprehensive workflow essential for chiplet design and today’s 3D IC architectures.

The multi-physics challenge: Known good die may not behave in 3D IC as stand alone!

Discover how Siemens’ EDA tackles the multi-physics challenge to achieve fast, accurate assembly-level physical verification.

Siemens introduces Innovator3D IC – a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing

Innovator3D IC – a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing

User2User 2024: xPD xSI PDK design enablement – Beyond Xpedition templates

PDK enablement beyond using Expedition templates, focusing on the challenges and solutions related to updating packaging tool functionality.

The role of AI-infused EDA solutions for semiconductor-enabled products and systems

Discover why semiconductor-enabled products and systems are demanding AI-infused solutions and how AI is changing the nature of semiconductor design.

Image showing physical design IP reuse with Xpedition Package designer

Embracing physical design IP reuse as a best practice

Efficiency in IC package design is becoming more important as design cycles shorten and complexity surges. One common approach to…

Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance

User2User 2024: Assembly verification flow for silicon interposers

In this User2User 2024 session Broadcom’s Suvarna Vikhankar presents “Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance”