Semiconductor Packaging

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Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Featured posts

3D IC design solutions: 2024 – Year in review

December 16, 2024

Welcome to a look back at a landmark year in 3D IC technology — 2024 was nothing short of revolutionary!…

By John McMillan
3 MIN READ
Text that says what's new in IC Packaging 2409 next to a stylized X

What’s new in IC Packaging 2409

September 19, 2024

The 2409 release is a landmark update in the field of electronic design automation (EDA), introducing a next-generation solution for…

By Keith Felton
3 MIN READ

Siemens introduces Innovator3D IC – a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing

July 31, 2024

Innovator3D IC – a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing

By John McMillan
4 MIN READ

Latest posts

The five keys to next-generation IC packaging design: Part 2

October 19, 2022

Multi-domain integration enables faster time to market for complex advanced semiconductor packages with a seamless integration of design and verification.

By Keith Felton
2 MIN READ
3D IC design engineer using gloved hands to inspect and verify components

Front-end architectural verification considerations for 3D IC design

October 11, 2022

So far in our 3D IC blog series, we’ve discussed efforts to create chiplet ecosystems, design workflow changes needed to…

By Heather George
18 MIN READ
what's new in Xpedition IC Packaging

What’s new in Xpedition Advanced IC Packaging release VX.2.12

September 19, 2022

The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which…

By Keith Felton
3 MIN READ

The Five Keys to Next-Generation IC Packaging Design: Part 1

September 7, 2022

Part 1: An advanced IC packaging design and verification solution For many applications, next generation IC packaging is the best…

By Keith Felton
2 MIN READ

3D IC verification requires a golden netlist that allows exceptions

August 29, 2022

With current 3D IC packaging technologies, since the system-level netlist (the 3D IC design intent) drives system-level LVS verification, designers…

By Tarek Ramadan
< 1 MIN READ

Megatrends of advanced IC packaging solutions 

August 25, 2022

Over last 2-3 years, everyone has been talking about Moore’s “Law” becoming invalid. Even if it does, we will continue…

By Keith Felton
3 MIN READ
IESF 2022

Learn about heterogeneous integration of semiconductors for autonomous driving, electric vehicle, and ADAS systems at the IESF 2022 automotive conference

August 18, 2022

IESF Automotive began 22 years ago and has been a must-attend event for automotive E/E design experts and executives throughout…

By Keith Felton
2 MIN READ
Evolution of 3D IC Architecture and the impact to design flows

Evolution of 3D IC Architecture and the impact to design flows

August 11, 2022

In our last blog about 3D IC, we discussed the models chiplet vendors need to provide System-in-Package (SiP) integrators to…

By Heather George
10 MIN READ
3D IC and the system-technology co-optimization (STCO) approach

3D IC and the system-technology co-optimization (STCO) approach

August 3, 2022

Semiconductor engineers aim to deliver best-in-class devices despite technology scaling and cost limitations of monolithic integrated circuit (IC) design. To…

By anthonymastroianni
2 MIN READ