​3D IC technology trends: how advanced IC packaging is changing the semiconductor industry

John McMillan (2.76)

From the drive towards miniaturization to the integration of complex functions through advanced packaging and 3D ICs, the future of IC technology is being reshaped before our very eyes. With the industry projected to reach a staggering $1 trillion market by 2030, companies are faced with the challenge of accelerating innovation while managing the ever-increasing complexities of 3D IC design and manufacturing. With that, let me welcome you to the 2025 Siemens EDA Podcast Series on 3D IC Chiplet Ecosystems, brought to you by the Siemens Thought Leadership Team. I’m your host, John McMillan. This podcast series dives into the exciting world of semiconductor chiplet integration and advanced technology platforms using 2.5 and 3D IC techniques. I’ll be talking to industry leaders and subject matter experts to discuss the latest 3D IC industry trends and roadmaps and uncover how the semiconductor industry is working diligently to make 3D IC mainstream.

In today’s podcast, I am excited to be joined by my special guest, Jan Vardaman, President of Tech Search International, to discuss the advanced packaging and heterogeneous integration roadmap for semiconductor scaling. Welcome, Jan, and thank you for taking the time to talk with me today. Before we dive into the discussion, please tell our listeners a little about yourself, your current role, and your background.

Jan Vardaman (1:21)

Well, our company is 37 years old, and we’ve been covering developments in packaging since before it became so popular. Our focus is entirely on advanced packaging, and the developments we’re seeing now are happening faster than ever. We’re very excited to discuss some of these topics with everyone.

John McMillan (1:50)

Great. So, as a company laser-focused on the semiconductor packaging market, what do you see as the main drivers for advanced integration heterogeneous or homogeneous silicon from both a technology and business point of view?

Jan Vardaman (2:05)

Well, cost is always a major driver. The reason we’re seeing so much interest in the idea of the chiplet is that it offers a new way to design an IC. We can no longer afford to fabricate everything as a monolithic die on the most expensive nodes. That being said, it doesn t mean we won t continue with monolithic die. If you can do it, you should. But there are many cases where part of the IC design doesn’t scale as well as the logic. So, why would you want to fabricate a large portion of that die in a very expensive leading-edge node, like a 5 or 3-nanometer node, when it could be fabricated in a legacy node to save money on your silicon fab costs?

It’s really about silicon fab cost and the idea of disaggregating the IC design, then putting it back together in the package to achieve the highest performance possible. In many cases, you can also achieve a more energy-efficient solution in terms of your picojoules per bit measurement.

John McMillan (3:35)

Gotcha. That’s really insightful. So, given this, are there any specific market segments and industries that are driving these activities? For example, we hear a lot about hyperscale AI and HPC (high-performance compute), but is that the whole picture, or is there a broader set of players and markets involved?

Jan Vardaman (3:57)

Well, there are other applications. Today, NVIDIA processors up until Blackwell were monolithic die designs packaged with HBM, which I’d consider a form of heterogeneous integration, where communication happens between the GPU and HBM. With the chiplet designs that have been implemented, you’ve seen many designs over the last several years from AMD for servers, desktops, and gaming. The arguments they’ve made for chiplet designs are that the savings on the silicon side make up for any additional cost for the package. It’s truly significant savings on the silicon side.

They have the ability to do this architecture internally with their capabilities. What many people want to see now is the ability to include third-party chiplet designs into their own design. The industry is working on this, but there are challenges especially around testing, communication between chiplets, and the protocols involved.

It will be interesting to see how things develop. But we’re certainly in an era where we’re moving in that direction. For instance, NVIDIA’s new GPU for AI uses a chiplet architecture in a new package from TSMC called CoWoS-L, which is an RDL interposer. AMD’s MI300 series, currently in production, is a chiplet design, and interestingly, that design uses 3D stacking and hybrid bonding, achieving impressive energy efficiency alongside outstanding performance.

So, we’re seeing a combination of both heterogeneous integration and chiplet design in the market. Each company has a different approach, depending on their internal capabilities, design philosophy, and tools. So, we’ll see a variety of different options moving forward.

John McMillan (6:49)

Yeah, gotcha. So clearly, there’s a much broader set of industry interests than what we typically hear about. Some of these industries and markets are different. Are they all looking for the same integration solution or platform, or do they have different needs that require different technologies or platforms?

Jan Vardaman (7:08)

Well, I think you’re referring to the packaging solutions. Everyone has a different approach depending on their particular supply chain and capabilities. For example, the MI300 series uses a silicon interposer, a CoWoS done turnkey by TSMC.

John McMillan (7:11)

Yeah.

Jan Vardaman (7:32)

You also see the new Blackwell and Hopper series using the silicon interposer, CoWoS. The new Blackwell uses CoWoS-L, as I mentioned, with an RDL interposer instead of a silicon interposer. If you look at other solutions, Amazon uses CoWoS-R, which is the RDL solution without bridges. CoWoS-L, on the other hand, has silicon bridges.

Intel prefers embedded bridge technology in the laminate substrate, which they use for some of their server products and high-end applications. So, there’s a variety of package options available. A chiplet is really the architecture the way you design the IC and it’s put into the package you choose based on your design philosophy and your supply chain.

John McMillan (8:42)

Gotcha. That makes it much clearer for me, and I hope for our listeners as well. There’s been a lot published recently about substrate materials silicon, RDL, glass core, flexible glass, organic interposer bridges, etc. Are these all competing against each other, or do they have specific applications? And if so, how should a design team choose one over the other?

Jan Vardaman (9:06)

Well, it all depends on what you’re trying to achieve. For example, using a silicon interposer or an RDL interposer still requires a buildup substrate, typically with a C4 bump. You have your die, interposer, and substrate. RDL structures can either have an embedded silicon bridge or not. These solutions are favored by AMD and NVIDIA for high-performance cases.

Intel has favored the EMIB solution, where the bridge is embedded in a laminate substrate, achieving higher density where the bridge is located. There’s been a lot of debate over which solution is the most cost-effective, but again, it depends on your design and other factors, including your supply chain.

A number of people are moving toward RDL interposers, as we believe this allows for pitch scaling to much higher densities than a laminate organic substrate. There’s also potential with silicon bridges, maybe with TSVs or other capabilities, allowing for finer pitch scaling. Ultimately, it’s about understanding your internal capabilities and what system-level performance you want to achieve.

At the end of the day, there’s no single packaging solution we can point to and say, This is it, because it depends on many different factors.

John McMillan (11:40)

Gotcha. Great conversation, Jan. Thanks for joining me today on the podcast and for sharing your knowledge on this exciting and fast-moving area of technology. Also, I’d like to take a moment to mention that Siemens Innovator 3D IC platform was named the winner of the prestigious 3D InCites 2025 Award for Technology Enablement.

Jan Vardaman (11:51)

Thanks so much.

John McMillan (12:04)

It was quite an honor. And if you’re not familiar with the Innovator 3D IC platform, it s an AI-enhanced co-design tool that ensures digital continuity through system-centric planning for die, interposer, package, and PCB design. It provides early insights into thermal, mechanical, and electrical performance, reducing redesign iterations, and accelerating development.

I hope you found this podcast educational and insightful. I certainly did, and I feel a lot more empowered now when I talk to designers about advanced semiconductor packaging. We’re out of time for now, but thank you for joining us. Be sure to check out the show notes to learn more about 3D IC and the Innovator 3D IC platform. Don t forget to subscribe so you don t miss the next episode of the 3D IC podcast.