User2User 2024: Assembly verification flow for silicon interposers
In this User2User 2024 session entitled “Assembly verification flow for silicon interposers with embedded deep trench capacitance” Suvarna Vikhankar, a VLSI design professional with over 20 years of experience in CPU and ASIC design including RTL to GDS and interposer design whose been driving the 2.5D silicon interposer design of the various cutting edge switching products at Broadcom for more than a decade discusses the intricate assembly level verification flow for silicon interposers with embedded deep trench capacitance.
Suvarna delves into the complexities of verifying multi-die strategies that involve various types of interposers and packaging, highlighting the need for specialized verification processes beyond standard procedures. Suvarna also explains Broadcom’s collaboration with Siemens to develop a comprehensive verification flow that addresses these advanced design challenges.
Individual die > interposer > package verification isn’t enough
Assembly level verification flow for a pure interposer and die solution is available, but what about eDTC (embedded deep trench capacitance)? eDTC is the distributive device which we add in the interposer – this is where Broadcom worked with Siemens to develop the verification flow for these devices.
Independently verifying each die/substrate per their foundry/OSAT rules doesn’t ensure the overall assembly yield is good or will perform as expected. If you see the verification of individual die, you can use a pure vanilla PV flow that can identify the problem and achieve verification on die level.
Die on interposer stacking validation
When you integrate this die on an interposer, either a silicon interposer or in the package, a single solution, will not work. You need to have something extra, something more to validate this type of stacking. The assembly level verification flow comes into the picture for these types of problems.
What is the problem: Assume the case of multi-vendor, substrate package: For example: Interposer from foundry X and organic substrate from OSAT Y. Neither the foundry nor the OSAT can provide a full system: LVS verification deck. It is up to the designer to verify the full system.
“In general, with every die/substrate added to a complex package, the risk of an error increases.
Besides typical shorts/opens, errors like wrong orientation, data translation issues are common.”
Suvarna Vikhankar – Broadcom
Embedded deep trench capacitance (eDTC)
At Broadcom eDTCs are added inside the substrate. They are integrated into the silicon interposer routing to improve signal and power integrity. Foundries support different eDTC types, but it depends on the application.
How to verify silicon interposer with eDTC?
Since these devices and interposer are passive – there are no active devices, as such, this type of connectivity exposed a problem, a substrate short when Broadcom was performing verification, and it was very hard to debug.
Siemens’s solution for silicon interposer with eDTCs
To address the substrate short problem Broadcom and Siemens co-developed an interposer LVS flow based on the xSI/Calibre 3DSTACK solution:
- Represent eDTCs instances in the system netlist
- Represent eDTCs instances in the assembly layout
- Develop full automation of the Calibre 3DSTACK runset generation out of xSI
To learn all about how the implementation of assembly level verification flow addresses the complexities introduced by multi-die strategies in semiconductor design and how the collaboration between Broadcom and Siemens on developing verification flows for eDTC showcases industry partnership in enhancing chip performance watch the video recording now available on-demand.
If you missed User2User 2024 or attended the event and want to watch the 3D IC sessions again, the library of videos is now available on-demand here: Click here
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