By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…
By Matthew Hogan and Derong Yan As we all know, during the final sign-off verifications of full chip system-on-chip (SoC)…
The recent surge in used car prices may have you wondering what is driving this upswing, and just how much…
By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for IC verification flows and electronic…
By Matthew Hogan How are you handling your reliability verification right now? Custom reliability verification? No reliability verification? How confident…
By Dina Medhat – Mentor, A Siemens Business Design rule waivers Maybe a design rule that made sense at 22nm…
By Matthew Hogan, Mentor Graphics Latch-up detection is challenging. Learn how automated LUP checks help you find and eliminate LUP…
By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you correct reliability issues while they…
By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings…
