reliability verification

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Cloud Computing Makes Overnight TAT Attainable

October 11, 2021

By Matthew Hogan and Derong Yan As we all know, during the final sign-off verifications of full chip system-on-chip (SoC)…

By Design With Calibre
3 MIN READ

Don’t hit a roadblock in automotive electronics reliability verification!

July 20, 2021

The recent surge in used car prices may have you wondering what is driving this upswing, and just how much…

By Design With Calibre
2 MIN READ

Turn IC verification challenge from a hard slog into a walk in the park by using static checks

May 19, 2021

By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for IC verification flows and electronic…

By Design With Calibre
2 MIN READ

Building a strong reliability foundation with Calibre PERC

March 9, 2021

By Matthew Hogan How are you handling your reliability verification right now? Custom reliability verification? No reliability verification? How confident…

By Design With Calibre
3 MIN READ

Do you have a reliable automated waiver process for reliability verification?

October 13, 2020

By Dina Medhat – Mentor, A Siemens Business Design rule waivers Maybe a design rule that made sense at 22nm…

By Design With Calibre
2 MIN READ
Context-Aware Latch-up Checking

Context-Aware Latch-up Checking

October 17, 2016

By Matthew Hogan, Mentor Graphics Latch-up detection is challenging. Learn how automated LUP checks help you find and eliminate LUP…

By Design With Calibre
5 MIN READ
Leveraging Reliability-Focused Foundry Rule Decks

Leveraging Reliability-Focused Foundry Rule Decks

August 12, 2016

By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you correct reliability issues while they…

By Design With Calibre
4 MIN READ
LEF/DEF IO Ring Check Automation

LEF/DEF IO Ring Check Automation

December 15, 2015

By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings…  

By Design With Calibre
5 MIN READ
Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

November 3, 2015

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks on multiple-power-domain and mixed-signal designs…

By Design With Calibre
4 MIN READ