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The virtuous cycle of silicon: How Siemens is accelerating the era of Physical AI with NVIDIA cuLitho

October 14, 2026

GPU-accelerated computational lithography with Siemens Calibre and NVIDIA cuLitho By Dr. Jim Shiely, Chief of Staff for Calibre Semiconductor R&D,…

By Calibre IC Design & Manufacturing
4 MIN READ

Why curvilinear OPC demands a new optimization approach 

August 24, 2026

The semiconductor industry’s transition to sub-5 nm nodes has fundamentally changed photomask design economics. For years, teams relied on rectilinear…

By Calibre IC Design & Manufacturing
6 MIN READ

Calibre IC manufacturing research for what comes next

August 3, 2023

By Germain Fenger Director of Product Management RET modeling, Calibre Semiconductor Manufacturing Solutions There is no rest in semiconductor manufacturing….

By Calibre IC Design & Manufacturing
3 MIN READ

A new method of scaling and efficiency for the semi-manufacturing flow

January 9, 2023

By Beth Martin Calibre sets sail on Kubernetes While most Calibre semi-manufacturing jobs still run on on-premises compute clusters using…

By Calibre IC Design & Manufacturing
3 MIN READ

Curves ahead for IC manufacturing

June 20, 2022

By John Sturtevant It turns out that the ideal mask pattern to print such a circle is in fact a…

By Calibre IC Design & Manufacturing
2 MIN READ
ECO Fill Can Rescue Your SoC Tapeout Schedule

ECO Fill Can Rescue Your SoC Tapeout Schedule

February 27, 2017

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and re-verify late-stage changes quickly, while…

By Calibre IC Design & Manufacturing
5 MIN READ
Will EUV Kill Multi-Patterning?

Will EUV Kill Multi-Patterning?

January 25, 2017

By David Abercrombie, Mentor Graphics Many people think EUV lithography means the end of multi-patterning. Do you?

By Calibre IC Design & Manufacturing
8 MIN READ
Creating An Accurate FEOL CMP Model

Creating An Accurate FEOL CMP Model

November 21, 2016

By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid FEOL CMP modeling helps designers and foundries predict CMP hotspots in advanced…

By Calibre IC Design & Manufacturing
9 MIN READ
The Route to Faster Physical Verification and Better Designs

The Route to Faster Physical Verification and Better Designs

February 24, 2015

By Nancy Nguyen and Jean-Marie Brunet, Mentor Graphics Using the most accurate and up-to-date signoff engine instead of a limited…

By Calibre IC Design & Manufacturing
4 MIN READ