ESD protection

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Do you need an automated ESD verification methodology for 2.5D/3D ICs? If so, read on…

July 8, 2021

By Dina Medhat Electrostatic discharge (ESD) events cause severe damage to unprotected integrated circuits (ICs). You already know that, of…

By Design With Calibre
2 MIN READ

Automated ESD protection verification for 2.5-3D ICs is now a reality

January 28, 2021

Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up? How about an automated method…

By Design With Calibre
2 MIN READ
Transistor level ESD verification in large SoC designs

Transistor level ESD verification in large SoC designs

October 31, 2016

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help

By Design With Calibre
4 MIN READ
LEF/DEF IO Ring Check Automation

LEF/DEF IO Ring Check Automation

December 15, 2015

By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings…  

By Design With Calibre
5 MIN READ