ESD protection verification in 2.5/3D ICs is HARD (or is it?) Our on-demand webinar has the answer

By Calibre Staff Electrostatic discharge (ESD) is a big worry for integrated circuit (IC) designers,…

Automated ESD protection verification for 2.5-3D ICs is now a reality

Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up?…

Help! I’m not an ESD expert! Reducing ESD verification complexity

By Abdellah Bakhali – Mentor, A Siemens Business If you’re not an ESD expert (and…

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation…

Leveraging Reliability-Focused Foundry Rule Decks

By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you…

Interconnect Robustness Depends on Scaling for Reliability Analysis

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness…

My Design’s Interconnect Has Enough Wire Width to Withstand ESD… Doesn’t It?

By Frank Feng, Mentor Graphics Electrostatic discharge can destroy a circuit, but designing adequate protection…