Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

Latest posts

Silicon Photonics Verification: A Light in the Tunnel

May 31, 2018

By Omar El-Sewefy – Mentor, A Siemens Business Do silicon photonics designs need new verification tools? Turns out, expanding established…

By Design With Calibre

2 MIN READ

Standing on the corner, waiting for my layout to load…

May 21, 2018

By Dennis Joseph – Mentor, A Siemens Business Ever had this happen? You start loading your GDS layout and go…

By Design With Calibre

2 MIN READ

Customizing a Calibre DRC HTML Report

April 26, 2018

Love the DRC HTML report you can generate with a push of a button from Calibre interface tools, but wish…

By Design With Calibre

< 1 MIN READ

P&R Designers— How to quickly analyze and debug signoff DRC errors in P&R, using the Calibre RVE interface

April 10, 2018

Want to quickly analyze and debug signoff DRC errors in P&R? The Calibre RVE multi-viewer function lets you sync multiple…

By Design With Calibre

2 MIN READ

IC designers: find your focus and priorities during DRC debug

April 5, 2018

By Srinivas Velivala – Mentor, A Siemens Business Layout design verification gets exponentially harder with each new process technology node….

By Design With Calibre

3 MIN READ

Highlights from SPIE – Successes and advancements over the past year

March 8, 2018

By Gandharv Bhatara – Mentor, A Siemens Business At the 43rd SPIE Advanced Lithography conference in San Jose that ran from…

By Design With Calibre

6 MIN READ

Calibre PERC electrical reliability verification – why you need it at every node

March 5, 2018

By Juan C. Rey, Vice President of Engineering, Calibre – Mentor, A Siemens Business If you’re not performing electrical reliability…

By Design With Calibre

3 MIN READ

Watch & Learn: Reducing Time-to-Support

February 26, 2018

By Srinivas Velivala – Mentor, A Siemens Business If you’re a chip designer or a CAD person trying to figure…

By Design With Calibre

4 MIN READ

Simplify and speed up early floorplan verification with incremental interface DRC

February 13, 2018

By James Paris – Mentor, A Siemens Business In early floorplan verification, incomplete blocks produce numerous interface errors. Incremental interface…

By Design With Calibre

3 MIN READ