Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

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Optimal ESD protection with Calibre PERC and Solido Simulation Suite

September 17, 2024

By Neel Natekar Integrated circuit (IC) reliability engineers face the dual challenge of ensuring robust electrostatic discharge (ESD) protection without…

By Design With Calibre
4 MIN READ

Cloud Flight Plans enable cost-effective use of the cloud for peak productivity

September 5, 2024

By Chris Clee You might ask, “What on Earth is a Cloud Flight Plan?” It’s a collection of best practices…

By Design With Calibre
4 MIN READ

Faster design verification with Calibre nmLVS Recon Compare

August 22, 2024

By Wael ElManhawy Layout versus schematic (LVS) comparison is a fundamental step in integrated circuit (IC) design verification. It ensures…

By Design With Calibre
4 MIN READ

Cracking the code: ensuring reliability and performance in IC design with EM/IR analysis

August 5, 2024

By Karen Chow and Joel Mercier Integrated circuits (ICs) are everywhere, powering everything from washing machines and TVs to medical…

By Design With Calibre
6 MIN READ

Shift left for more efficient block design and chip integration

July 26, 2024

Block/chip integration is a lot more complicated than it gets credit for. On the face of it, chip integration just…

By Design With Calibre
6 MIN READ

Speeding up early design rule checking with Calibre nmDRC Recon

June 5, 2024

By John Ferguson and Nermeen Hossam Chip designers are very aware of how time-consuming early design rule checking (DRC) can…

By Design With Calibre
4 MIN READ

Automated analysis-based layout enhancements reduce power grid voltage drops during place & route: A case study with Google

May 29, 2024

By Jeff Wilson Power isn’t just a small factor in the IC design arena—it’s a cornerstone. Design teams work to…

By Design With Calibre
4 MIN READ

Accelerate IP design cycles and reduce costs with Calibre design stage verification

May 6, 2024

By Terry Meeks In the fast-paced world of semiconductor design, time is a critical asset. One way IC designers save…

By Design With Calibre
5 MIN READ

Balancing performance vs. debuggability in LVS circuit verification

April 23, 2024

By Wael ElManhawy Circuit verification engineers face ever more challenges as semiconductor technology evolves towards smaller process nodes and integrated…

By Design With Calibre
3 MIN READ