Find high resistance faster in P2P violations with interactive P2P analysis

By Slava Zhuchenya So your net trace has too much parasitic resistance. Where is it coming from? You ran your…

Struggling to verify the reliability of your multiple-power-domain designs?

By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize…

Plug and Play ESD protection

By Mark Tawfik Electrostatic discharge (ESD) is the discharge of static electrical current when two objects come into contact. One…

What’s an ESD design window, and why do I care?

By Derong Yan As we move to advanced semiconductor process nodes, electrostatic discharge (ESD) issues have become more critical in…

A touchy subject: RF IC layout verification

By Neel Natekar Radio frequency (RF) circuitry is an essential component of many of the critical applications we now rely…

DRC voltage text annotations: Manually placed texts can be wrong!

By Abdellah Bakhali System-on-chip (SoC) designs often use multiple intellectual property (IP) blocks from multiple IP providers. Each IP provider…

Do you trust the reliability of your 2.5D/3D IC package designs?

By Dina Medhat 2.5D/3D ICs have become an innovative solution for many design and integration challenges. Basic physical verification for…

Reliability checking for memory circuit design doesn’t have to destroy your eyesight!

By Hossam Sarhan Memory blocks contain sensitive analog circuits that are crucial for the proper functionality of the whole design….

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…