Package it up!

Package it up!

By Tarek Ramadan, Mentor Graphics Uniting package design environments with SoC physical verification tools ensures the necessary co-design and verification…

Mentor tools now certified on TSMC 12 FFC or 7 nm

Mentor tools now certified on TSMC 12 FFC or 7 nm

Planning a design using TSMC’s new 12 FFC or 7 nm V1.0 processes? Good news, the entire Mentor Graphics Calibre…

Clear your calendar – U2U is coming!

Clear your calendar – U2U is coming!

Take a look at what you’ll find at this year’s Mentor’s user group event located at the Santa Clara Marriott…

Are You Wasting Your SRAM Memory Redundancy?

Are You Wasting Your SRAM Memory Redundancy?

By Simon Favre, Mentor Graphics Want to know if your SRAM redundant memory elements are actually useful, or a waste…

See you at TSMC 2017!

See you at TSMC 2017!

It’s that time of year again…

ECO Fill Can Rescue Your SoC Tapeout Schedule

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and re-verify late-stage changes quickly, while…

What to see at SPIE 2017

What to see at SPIE 2017

It is time again for the SPIE Advanced Lithography conference.

DFM Line-End Enhancement with Calibre Pattern Matching

DFM Line-End Enhancement with Calibre Pattern Matching

Using Calibre Pattern Matching to add line-end extensions to a design is a simple way to improve yield and reliability,…

How to choose LVS box flow

How to choose LVS box flow

How do you decide which kind of LVS BOX flow makes sense for what you want to accomplish? Watch this…