Portable Stimulus and VIP: Like a Hand in a Glove

One of my favorite things about DAC is the ability to share with so many of you some details of…

Circuit board with chip and binary data depicting interface Protocol Verification

Announcing Avery UCIe 2.0 Verification IP from Siemens EDA

Announcement: Siemens EDA are excited to announce availability of our Verification IP products for UCIe version 2.0, coincident with today’s…

Verification Challenges and Solutions for Multi-Die Systems (UCIe) 

Introduction Multi-die systems accelerate the scaling of system functionality, reduce risk, and facilitate the creation of new product variants. However,…

Accelerating Verification of Computational Storage Designs (NVMe)

Introduction Computational storage is revolutionizing data storage by embedding computational capabilities within storage devices, significantly boosting system efficiency by reducing…

Accellera Proposes a New Working Group

Accellera Proposes a New Working Group

Accellera to explore the need for an IP Security Assurance Standard In the era of SoC design where major design…

Design & Verification IP Forum 2017

Design & Verification IP Forum 2017

VIP: Accelerating SoC Design Verification Your SoC designs have grown more complex, not just by the sheer number of transistors…

No to Know VIP – Part 3

No to Know VIP – Part 3

Thus far we have talked about the importance of having a VIP which is easy to connect to the DUT…

UVM Forum 2015 LIVE!

UVM Forum 2015 LIVE!

Verification Academy Brings “UVM Live” to the Santa Clara Convention Center For everyone involved in the functional verification of electronic…

Verification Horizons: The DAC 2015 Issue

Verification Horizons: The DAC 2015 Issue

If you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed…