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Part 10: The 2016 Wilson Research Group Functional Verification Study

Part 10: The 2016 Wilson Research Group Functional Verification Study

October 31, 2016

IC/ASIC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2016…

By Harry Foster
3 MIN READ
Part 6: The 2016 Wilson Research Group Functional Verification Study

Part 6: The 2016 Wilson Research Group Functional Verification Study

September 21, 2016

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2016 Wilson…

By Harry Foster
5 MIN READ
IEEE-SA EDA & IP Interoperability Symposium

IEEE-SA EDA & IP Interoperability Symposium

October 7, 2015

Design and verification flows are multifaceted and predominantly built by bringing tools and technology together from multiple sources.   The tools…

By Dennis Brophy
4 MIN READ
Part 10: The 2014 Wilson Research Group Functional Verification Study

Part 10: The 2014 Wilson Research Group Functional Verification Study

July 27, 2015

IC/ASIC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2014…

By Harry Foster
3 MIN READ
It’s Time for a New Verification Debug Data API (DDA)

It’s Time for a New Verification Debug Data API (DDA)

June 4, 2015

Learn more about DDA at DAC At DAC – Mentor Graphics and Cadence Design Systems are coming together to usher…

By Dennis Brophy
3 MIN READ
Part 6: The 2014 Wilson Research Group Functional Verification Study

Part 6: The 2014 Wilson Research Group Functional Verification Study

June 3, 2015

FPGA Verification Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the…

By Harry Foster
4 MIN READ
DVCon India: A Smashing Hit!

DVCon India: A Smashing Hit!

October 9, 2014

DVCon India, held in September 2014 in Bangalore, built on the Indian SystemC User Group meeting events and added a…

By Dennis Brophy
3 MIN READ
The FPGA Verification Window Is Open

The FPGA Verification Window Is Open

May 7, 2014

My Feb. 4 post introduced Mentor Graphics’ three-step FPGA verification process intended to help design teams get out of the…

By Danny Santoro
< 1 MIN READ
Just because FPGAs are programmable doesn’t mean verification is dead

Just because FPGAs are programmable doesn’t mean verification is dead

February 4, 2014

Marketing teams at FPGA vendors have been busy as the silicon nanometer geometry race escalates. Altera is “delivering the unimaginable”…

By Danny Santoro
2 MIN READ