How To Connect Your Testbench to Your Low Power UPF Models

Face facts: power supply nets are now effectively functional nets, but they are typically not…

Part 10: The 2016 Wilson Research Group Functional Verification Study

ASIC/IC Language and Library Adoption Trends This blog is a continuation of a series of…

Part 6: The 2016 Wilson Research Group Functional Verification Study

FPGA Language and Library Trends This blog is a continuation of a series of blogs…

Prologue: The 2016 Wilson Research Group Functional Verification Study

This is the first in a series of blogs that presents the findings from our…

IEEE-SA EDA & IP Interoperability Symposium

Design and verification flows are multifaceted and predominantly built by bringing tools and technology together…

Part 10: The 2014 Wilson Research Group Functional Verification Study

ASIC/IC Language and Library Adoption Trends This blog is a continuation of a series of…

It’s Time for a New Verification Debug Data API (DDA)

Learn more about DDA at DAC At DAC – Mentor Graphics and Cadence Design Systems…

DVCon India: A Smashing Hit!

DVCon India, held in September 2014 in Bangalore, built on the Indian SystemC User Group…

The FPGA Verification Window Is Open

My Feb. 4 post introduced Mentor Graphics’ three-step FPGA verification process intended to help design…