It’s my favorite time of year again—DVCon! And I believe that the DVCon 2015 technical program committee has put together…
Accellera Approves Creation of Portable Stimulus Working Group At DVCon 2014, Mentor Graphics proposed Accellera launch an exploratory exercise, called…
FPGA Design Trends In my previous blog, I introduced the 2014 Wilson Research Group Functional Verification Study (click here). The objective…
This blog is a continuation of a series of blogs that present the highlights from the 2014 Wilson Research Group…
This is the first in a series of blogs that presents the findings from our new 2014 Wilson Research Group…
“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. …
SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS…
From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year…
Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM). …
