“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. …
SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS…
From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year…
Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM). …
DVCon is always one of my favorite events in our industry, and I am proud to let you know that…
MENTOR GRAPHICS AT ARM TECHCON This week ARM® TechCon® 2013 is being held at the Santa Clara Convention Center from…
Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs that present the highlights…
Language and Library Trends This blog is a continuation of a series of blogs that present the highlights from the…
You don’t need a graphic like the one below to know that multi-core SoC designs are here to stay. This one…
