Understanding and Minimizing Study Bias

Understanding and Minimizing Study Bias

This blog is a continuation of a series of blogs that present the highlights from the 2014 Wilson Research Group…

Prologue: The 2014 Wilson Research Group Functional Verification Study

Prologue: The 2014 Wilson Research Group Functional Verification Study

This is the first in a series of blogs that presents the findings from our new 2014 Wilson Research Group…

Who Knew VIP?

Who Knew VIP?

“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. …

SystemVerilog Testbench Debug – Are we having fun yet?

SystemVerilog Testbench Debug – Are we having fun yet?

SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS…

Supporting A Season of Learning

Supporting A Season of Learning

From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year…

Accellera Approves UVM 1.2

Accellera Approves UVM 1.2

Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM). …

DVCon 2014 Issue of Verification Horizons Now Available

DVCon 2014 Issue of Verification Horizons Now Available

DVCon is always one of my favorite events in our industry, and I am proud to let you know that…

Happy Halloween from ARM  TechCon

Happy Halloween from ARM TechCon

MENTOR GRAPHICS AT ARM TECHCON This week ARM® TechCon® 2013 is being held at the Santa Clara Convention Center from…

Part 10: The 2012 Wilson Research Group Functional Verification Study

Part 10: The 2012 Wilson Research Group Functional Verification Study

Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs that present the highlights…