Portable Stimulus: A Small Step in Standardization

Portable Stimulus: A Small Step in Standardization

Accellera Approves Creation of Portable Stimulus Working Group At DVCon 2014, Mentor Graphics proposed Accellera launch an exploratory exercise, called…

Part 1: The 2014 Wilson Research Group Functional Verification Study

Part 1: The 2014 Wilson Research Group Functional Verification Study

FPGA Design Trends In my previous blog, I introduced the 2014 Wilson Research Group Functional Verification Study (click here). The objective…

Understanding and Minimizing Study Bias (2014 Study)

Understanding and Minimizing Study Bias (2014 Study)

This blog is a continuation of a series of blogs that present the highlights from the 2014 Wilson Research Group…

Prologue: The 2014 Wilson Research Group Functional Verification Study

Prologue: The 2014 Wilson Research Group Functional Verification Study

This is the first in a series of blogs that presents the findings from our new 2014 Wilson Research Group…

Who Knew VIP?

Who Knew VIP?

“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. …

SystemVerilog Testbench Debug – Are we having fun yet?

SystemVerilog Testbench Debug – Are we having fun yet?

SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS…

Supporting A Season of Learning

Supporting A Season of Learning

From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year…

Accellera Approves UVM 1.2

Accellera Approves UVM 1.2

Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM). …

DVCon 2014 Issue of Verification Horizons Now Available

DVCon 2014 Issue of Verification Horizons Now Available

DVCon is always one of my favorite events in our industry, and I am proud to let you know that…