I Do It …

I Do It …

… To Advance Technology for Humanity  It is a humbling honor to have been elected chair of the IEEE Standards…

SystemVerilog: A time for change? Maybe not.

SystemVerilog: A time for change? Maybe not.

The SystemVerilog IEEE 1800-2009 Language Reference Manual (LRM) was published a few months ago with an unprecedented 472 updates. That’s…

A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA

A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA

I’m excited. I’ve had the pleasure of knowing Cliff Cummings for many years, and I was honored a couple of…

Truth in Labeling: VMM2.0

Truth in Labeling: VMM2.0

I see that Synopsys has finally released VMM1.2. Congratulations, guys. There will be plenty of opportunity over the coming weeks…

IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download

IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download

Just in time for the holidays!  🙂 IEEE Std. 1800™-2009, aka SystemVerilog 2009, is ready for purchase and download from…

Full House – and this is no gamble!

Full House – and this is no gamble!

SystemVerilog proved to be a “royal flush” of a reason for 100’s of people to gather together. Leaving poker references…

SystemVerilog: The finer details of $unit versus $root.

SystemVerilog: The finer details of $unit versus $root.

Another installment of “Longwinded Answers to Frequent SystemVerilog Questions: $root versus $unit” Believe me – I tried to make this…

SystemVerilog Coding Guidelines

SystemVerilog Coding Guidelines

I have lots of blog entries about 95% ready to publish. This entry is from an e-mail I wrote a…

The Language versus The Methodology

The Language versus The Methodology

I’ve been around simulation and synthesis languages for a while; back when you needed an NDA to see the Verilog…