UVM-EA (Early Adopter) Starter Kit Available for Download

UVM-EA (Early Adopter) Starter Kit Available for Download

Companion UVM-EA OVM Compatibility Overlay Kit Available for Download Mentor Graphics has made available its UVM-EA starter kit to promote…

Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)

Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)

Requirements set for Accellera UVM-EA (Early Adopter) Release This was a productive week for Accellera. After months of discussions, the…

The Art of Deprecation

The Art of Deprecation

At a recent SystemVerilog requirements gathering meeting,I was quite amused to see “deprecating features” come out as one of the…

IEEE Standards Meetings in India

IEEE Standards Meetings in India

EDA & VLSI Standards Focus Meeting on 12 March 2010  As part of its continuing program to reach out to…

I Do It …

I Do It …

… To Advance Technology for Humanity  It is a humbling honor to have been elected chair of the IEEE Standards…

SystemVerilog: A time for change? Maybe not.

SystemVerilog: A time for change? Maybe not.

The SystemVerilog IEEE 1800-2009 Language Reference Manual (LRM) was published a few months ago with an unprecedented 472 updates. That’s…

A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA

A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA

I’m excited. I’ve had the pleasure of knowing Cliff Cummings for many years, and I was honored a couple of…

Truth in Labeling: VMM2.0

Truth in Labeling: VMM2.0

I see that Synopsys has finally released VMM1.2. Congratulations, guys. There will be plenty of opportunity over the coming weeks…

IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download

IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download

Just in time for the holidays!  🙂 IEEE Std. 1800™-2009, aka SystemVerilog 2009, is ready for purchase and download from…