In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should…
It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the…
Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is…
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced…
Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about…
Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on…
System Standards Worlds Initiate Unification Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC…
How do your favorites rank? Have you ever wondered how popular the different IEEE standards for electronic design automation are?…
Language and Library Trends This blog is a continuation of a series of blogs, which present the highlights from the…
