The IEEE’s Most Popular EDA Standards

The IEEE’s Most Popular EDA Standards

How do your favorites rank? Have you ever wondered how popular the different IEEE standards for electronic design automation are?…

Part 8: The 2010 Wilson Research Group Functional Verification Study

Part 8: The 2010 Wilson Research Group Functional Verification Study

Language and Library Trends This blog is a continuation of a series of blogs, which present the highlights from the…

Language Transitions: The Dawning of Age of Aquarius

Language Transitions: The Dawning of Age of Aquarius

Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages OK, maybe it is not the Dawning of the Age…

Parameterized Classes, Static Members and the Factory Macros

Parameterized Classes, Static Members and the Factory Macros

Somebody asked me a simple question: Why do need two different macros (`ovm_object_utils and `ovm_object_param_utils) to register classes with the…

IEEE Standards in India

IEEE Standards in India

IEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi I, along with several other individuals, will participate…

Accellera Approves New Co-Emulation Standard

Accellera Approves New Co-Emulation Standard

Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the…

SystemVerilog Coding Guidelines: Package import versus `include

SystemVerilog Coding Guidelines: Package import versus `include

Another frequently asked question: Should I import my classes from a package or `include them? To answer this properly, you…

UVM: Joint Statement Issued by Mentor, Cadence & Synopsys

UVM: Joint Statement Issued by Mentor, Cadence & Synopsys

DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys The full statement can be read at EDA…